Multiplexers are used in a wide variety of applications to select one or more of several different inputs as an output. In some applications, different voltage levels are provided as different inputs to a circuit, to provide different functionality depending on the voltage level input that is selected by the multiplexer. For example, in some integrated circuit applications such as Flash or EEPROM memories, there is a need to have, on the same circuit net, one given voltage level during one operation (such as writing) and another voltage level during a different operation (such as reading). Analog applications may also require multiple voltage level supplies to output on a common net.
In some applications, the inputs can have very different voltage levels. Digital control signals are typically the most suitable signals to select which of the inputs is provided to the circuit. In many such circuits, the output voltage is desired to be identical to the selected input voltage, with little or no voltage drop caused by the multiplexer. In addition, high reliability of the multiplexer is desired, so that the selected input voltage is output with minimal variation and fluctuations during dynamic behavior (such as a different selection of input to the multiplexer).
FIG. 1 is a schematic diagram of one type of prior multiple voltage multiplexer 10. Multiplexer 10 receives multiple voltage inputs, each input providing a different voltage value. For example, inputs V1, V2 and V3 can be 1.2 volts, 5 volts, and 15 volts, respectively. Digital control signals CTRL1, CTRL2, and CTRL3 are used to select the desired input voltage to be output by the multiplexer, where these signals select voltages V1, V2, and V3, respectively, to be output. One control signal is set to a high level to allow the associated voltage to be output, while the other control signals are set low.
Each control signal is input to a level shifter 12a, 12b, or 12c, which also receives an level input of the voltage V1, V2, or V3 as shown. When the control signal is low, a level shifter 12 provides a low signal (zero voltage) as the output signal OUT1, OUT2, or OUT3. When the control signal is high, the input voltage V1, V2, or V3 is provided as the output OUT1, OUT2, or OUT3 of the level shifter, respectively. This allows a control signal of any digital voltage to be shifted to the proper voltage level needed for the multiplexer to function.
A native transistor device 14a, 14b and 14c is connected to the OUT1, OUT2, and OUT3 signals, respectively, at the gates of the transistors. The voltage V1, V2, or V3 is connected to the source of the transistor 14a, 14b, 14c, respectively, and the drains of the transistors are connected to a VOUT output node. These native devices have the property of having a threshold voltage of Vt close to −0.1 volts. This means that these devices are off with a gate to source voltage below −0.1 volts and on with a gate to source voltage above −0.1 volts.
If voltage V1 is desired to be transferred onto VOUT, then the CTRL1 signal is asserted (set high). Level shifter 12a outputs the voltage V1 to the gate of the transistor 14a, and the voltage V1 on the source is passed to VOUT with a voltage drop equivalent to the native transistor threshold voltage of transistor 14a, including the body effect of the transistor. This body effect can be considered negligible if V1 stays around 1 or 2 volts. However, the body effect can reach 0.3 volts as soon as V1 reaches 15 volts. The other pass transistors 14b and 14c are off because their gate to source voltage is −VOUT or −V2 or −V3, which is less than −0.1 volts.
Thus, if an input voltage level is high, such as 12 or more volts, the body effect is not negligible and provides a significant voltage drop on the output voltage. This characteristic creates a significant disadvantage for the multiplexer of FIG. 1 in many applications, because the output signal has a different value than the input voltage signal to the multiplexer (signal integrity loss).
FIG. 2 is schematic illustration of a different prior multiple voltage multiplexer 20. As in the circuit of FIG. 1, different voltage inputs V1, V2, and V3 can be input to the multiplexer 20, and one of these inputs can be selected to be output onto the VOUT output node. The control signals CTRL1, CTRL2, and CTRL3 similarly select which of the input voltages is propagated onto the VOUT node.
In multiplexer 20, inverters 22a, 22b, and 22c are connected to the control signals CTRL1, CTRL2, and CTRL3, respectively. The inverted control signal is input to a level shifter 24a, 24b, or 24c, which provides a signal OUT1, OUT2, or OUT3, respectively. As in the circuit of FIG. 1, the level shifters 24a, 24b, and 24c are provided with an input carrying the voltage V1, V2, or V3, respectively. Each level shifter output signal is connected to the gate of a transistor 26a, 26b, or 26c, which is connected to voltage V1, V2, or V3 at its source, respectively, and to the VOUT output node at its drain. Transistors 26a, 26b, and 26c are PMOS transistors, non-native devices that can hold the maximum driven input voltage, and have their bulk terminals connected to their drains.
If voltage V1 is desired to be transferred to VOUT, then the CTRL1 signal is asserted (set high) and the other control signals are set low. The CTRL1 signal is inverted by inverter 22a to a low signal that is input to level shifter 24a, and level shifter 24a outputs a zero voltage to the gate of the transistor 26a. This allows the voltage V1 to pass to VOUT without any voltage drop by the transistor 26a. At this time, the bulk of the transistor 26a, which is connected to the VOUT node, is lower than V1 for a given amount of time until V1 is transferred to VOUT. Depending on this delay (based on the VOUT load and initial Vbulk voltage) or on the dynamic behavior of the VOUT node when switching to different voltage inputs, the transistor 26a can stay with a bulk to source voltage much below (−0.6) volts. This biasing injects a strong current into the n-well of the transistor 26a, triggering PNP bipolar transistor behavior, and resulting in a short or long term reliability issue of the transistor 26a so that the transistor may not function properly under these conditions. For reliable transistor operation, it is desired to keep the PMOS bulks at Vb+0.5v>Vs, where Vb is the bulk voltage and Vs is the source voltage; this is especially true when VOUT is switching from one voltage level to another. Multiplexer 20 does not maintain such voltages. In addition, this second scheme does not work if V1 is selected (by signal CTRL1) and V2 is greater than V1. In such a case, VOUT is approximately equal to V1, and Vbs of transistor 26a is (V1−V2), which is less than zero. If (V1−V2) is less than about −0.5 volts, this will lead to a reliability issue. In other words, this second scheme requires specific input voltage level control for V1, V2, and V3.
Thus, both these existing multiplexer designs provide disadvantages, either in the form of an undesired voltage drop, or in unreliable behavior under certain conditions.
Accordingly, what is needed is a multiplexer that can multiplex multiple inputs providing different voltages, without any significant voltage drop and without reliability issues. The present invention addresses such a need.